Radio Frequency Interference (RFI) often causes performance degradation in high-speed signals such as those under the universal serial bus (USB) 3, high definition multimedia interface (HDMI), display port (DP), and enhanced DP (eDP) standards. For example, USB3 running at five gigabits per second (Gbps) can cause wireless communication user experience issues. Therefore, the use of common mode choke (CMC) filters in high-speed signals is highly recommended to mitigate RFI.
Traditionally, original design manufacturers (ODMs) use discrete CMC filters (CMGs) to suppress the common-mode noise and avoid possible degradation of wireless signals. However, discrete CMGs add significantly to the bill of materials (BOM) costs since they are typically about ten times more expensive than other passive surface mount technology (SMT) components, such as resistors and capacitors.
Printed circuit board (PCB) based CMC technology has been developed as an alternative to discrete CMGs, with the goal of helping customers significantly save on BOM costs while at the same time guaranteeing platform designs that are robust against RFI. This customized solution has been implemented in multiple ultrabook and tablet-based platforms having six-, eight-, and ten-layer PCBs.
Recently, the PCB-CMC solution has developed for four-layer boards, which are typically used in lower cost platforms, desktops, and all-in-one (AIO) systems. FIG. 1 shows a PCB-CMC four-layer design 50 with above—1 deciBel (dB) differential insertion loss (SDD21) up to 5 gigaHertz (GHz) and −10 dB filter bandwidth from 1.8 GHz to 9 GHz. SDD21, an industry notation for differential insertion loss, describes how the differential signal changes after transmission through a channel (the electrical path of the signal). SDD21 thus quantifies how well the channel transmits the differential signal.
The design of FIG. 1 effectively mitigates RFI. However, the differential pair of this design has a high return loss: about −10 dB from 4 GHz to 5 GHz, which is much higher than the design specification of −15 dB. This high return loss negatively impacts the high speed I/O signal integrity and hinders the adoption of the four-layer PCB-CMC.
The electrical pathway of a signal between layers of a multiple-layer printed circuit board (PCB) is known as a via. Thus, the channel being measured includes the via or vias when present. Studies show that high inductance of the vias is the major contributor to the impedance mismatch and consequently the high reflection characterizing the four-layer PCB-CMC designs.
To suppress the high reflection within the frequency range of interest, i.e., from direct current (DC) to 5 GHz, one solution is to increase the drill diameter to reduce inductance and hence lower the impedance mismatch. However, due to manufacturing limitations, the change of the drill size cannot be dramatic. Therefore, the improvement achieved by using this solution is small.
FIG. 2 is a graph 150 plotting frequency (GHz) versus magnitude (dB) for two drill diameters, 8 mil and 10 mil (one mil is one thousanth of an inch). Both 8 mil and 10 mil designs have a large differential return loss, known in industry parlance as SDD11: around −10 dB from 4 GHz to 5 GHz. SDD11 describes the differential signal that reflects back to the source, when a differential signal is incident at the beginning of the channel. Like differential insertion loss (SDD21), differential return loss (SDD11) provides a characteristic of the channel being measured, in this case, its impedance profile.
Another solution for avoiding a high return loss in four-layer PCB-CMC designs is to reduce the anti-pad size of the vias. An anti-pad is a clearance in a copper plane that will allow a drilled hole to pass through the copper plane without making a connection to an electrical pathway. A smaller anti-pad size results in a smaller current loop and, consequently, a smaller inductance.
FIG. 3 is a second graph 200 plotting frequency (GHz) versus magnitude (dB) for anti-pad diameters of 26 mil and 32 mil. Measurements for differential mode return loss (SDD11), differential mode insertion loss (SDD21), and common mode insertion loss (SCC21) are provided for two antipad sizes, 26 mil antipad (solid lines) and 32 mil antipad (dashed lines).
As highlighted in the oval at the top of the graph, a 26 mil anti-pad can reduce the differential return loss (SDD11) by around 3 dB from 2.5 GHz to 6 GHz. The darker lines in the oval show the differential mode return loss (which can be thought of as transmitted energy) for a 26 mil antipad (solid) and a 32 mil antipad (dashed). The lighter lines in the oval show the differential mode insertion loss (which can be thought of as reflected energy) for the two antipads. Both differential mode return loss (reflected energy) and differential mode insertion loss (transmitted energy) increases as the value becomes more negative.
The oval covers the frequency range of about 4.6 GHz-5 GHz, where the differential mode return loss is −5 dB for the 32 mil antipad versus −8 dB for the 26 mil antipad. Since the differential mode return loss increases as the value becomes more negative, the differential mode return loss is higher for the 26 mil antipad. The differential mode insertion loss is −3 dB for the 32 mil antipad versus −2 dB for the 26 mil antipad. Since the differential mode insertion loss increases as the value becomes more negative, the differential mode insertion loss is lower for the 26 mil antipad. Because it maximizes the SDD11 and minimizes the SDD21 (most of the energy gets transmitted, not reflected) relative to the 32 mil antipad, the 26 mil antipad is preferred for the indicated frequency range. A loss increase is defined herein as more negative whereas a loss reduction is more positive.
Despite these benefits, manufacturing constraints also limit the improvement achieved by reducing the anti-pad size. With 26 mil anti-pads implemented in four-layer PCB-CMC, the return loss is still 5 dB higher than the specification from 4 GHz to 5 GHz.
Thus, there is a continuing need for a solution that overcomes the shortcomings of the prior art.